1. Field of the Invention
The present invention generally relates to solid state imaging devices equipped with charge coupled devices (CCD""s) and, more particularly, the present invention relates to solid state imaging devices which are configured for electronic zooming and to methods of fabricating such devices.
Priority is claimed to Korean patent application No. 2000-27810, filed May 23, 2000, the contents of which are incorporated herein in their entirety.
2. Description of the Related Art
Generally, solid state imaging devices are semiconductor devices which sense external images and convert the thus sensed images into image signals. Images are typically captured through lenses and converted into image signals on a pixel by pixel basis. These image pixel signals are then amplified for visual reconstruction on a television or other display apparatus.
FIG. 1 illustrates the basic construction of a solid state imaging device. This diagram depicts a top view of the device, which is typically contained in a active area of a semiconductor substrate that is rectangular and defined by a surrounding field insulating region (not shown). Light receiving parts 10 are arranged in a matrix as shown and include respective photodiodess. Vertical transfer stages 20 extend parallel to each other in a column direction and are arranged between columns the light receiving parts 10. The vertical transfer stages 20 are commonly coupled at one end to a horizontal transfer stage 30 that extends lengthwise in a direction perpendicular to the vertical transfer stages 20.
The photodiodes of the light receiving parts 10 are each configured by a P-N junction formed in the semiconductor substrate. For example, a P-type impurity diode layer is formed over a surface layer of the semiconductor substrate, and a buried N-type impurity diode layer is formed thereunder. A periphery of the N-type impurity diode layer is surrounded by the P-type impurity layers, being isolated therefrom. When a photodiode formed in a light receiving part 10 senses external light, photoelectrons are generated to condense charges. These charges are transferred to a vertical transfer stage 20 and then gradually transferred to the horizontal transfer stage 30 in response to a clock signal applied to the vertical transfer stage. The transferred charges to the horizontal transfer stage 30 are transferred to a circuit of an output unit in response to a clock signal that is rapidly applied to the horizontal transfer stage 30, thereby forming an amplified image signal.
The aforementioned clock signal is transferred to the horizontal transfer stage 30 through a gate electrode that is separated from a thin gate insulating layer. A voltage is divided into the specific steps, which are sequentially and periodically applied to the gate electrode. The gate electrode also is divided into parts that transfer charges of a predetermined width to the circuit of an output unit, forming a stepped potential thereby.
The amount of charges condensed in the light receiving parts 10 of the solid state imaging device is dependent upon an intensity or quantity of incident light. In some cases, charges which are produced in the light receiving parts 10 from a large quantity of incident light and transferred from the vertical transfer stage 20 to the horizontal transfer stage 30, are so excessive as to prevent the proper transfer of charges from the horizontal transfer stage to an output unit.
An example of a structure for processing excessive charges transferred to a transfer stage is disclosed in U.S. Pat. No. 4,504,848. In the disclosed structure, a drain for discharging charges of a light receiving part is formed to produce remnant charges in an established active region for forming the light receiving part. A voltage barrier region is operable with a voltage whose level is identical to that of the light receiving part, and is set between a drain region and a general light receiving part. The drain is doped with one type of impurities whose concentration is higher than that of the light receiving part, and the barrier region has additive impurities of the other type.
In such a structure, although a voltage is applied equivalently to a general light receiving part and a barrier layer, the barrier layer is influenced less than the general light receiving part by the voltage. Within a constant voltage range, a charge processing capacity in a transfer mode (wherein a voltage is applied to a gate) is higher than that in a light receiving mode (wherein the voltage is applied thereto). If the charge processing capacity is lowered at a specific position of the vertical transfer stage, a vertical error can be prevented. Here, the vertical error is a brightness decay phenomenon at a region over the specific position.
A structure for discharging remnant charges to a drain through a barrier is disclosed in U.S. Pat. No. 5,455,443. In this case, a buffer zone is formed between a drain for discharging remnant charges and a barrier region to discharge the remnant charges. The buffer zone prevents the drain from discharging the remnant charges to vertical and horizontal transfer stages resulting from transient potential instability. In other words, charges are not transferred to a position where they must normally be transferred for images, preventing distortion of a display screen.
Another type of phenomenon relating to excessive charges occurs, for example, during special functions of an image pickup apparatus. In a conventional image pickup operation, the horizontal transfer stage cannot process photoelectrons that are excessively transferred while carrying out an electronic zooming function. This causes distortion of an upper part of a screen that is zoomed in.
Referring to FIG. 2, electronic zooming functions to output only a zoom area 40 to the exclusion of a remaining area of an overall pixel area 50 of a solid state imaging device. In a zoom mode, signal line electrons of intervals A and B are transferred in a short time to a horizontal transfer stage 30 in response to a clock signal of a fast vertical transfer stage. These electrons are discarded through reset-step transfer in which a screen is not composed. Electrons of a signal line in a zoom interval are transferred to a horizontal transfer stage 30 in response to a clock signal of a vertical transfer stage that is later than a general processing. Except for electrons in a column of the zoom area 40, signal line electrons of a zoom interval are processed so that a screen is not composed by a high-frequency horizontal clock signal or other circuit arrangement. In proportion to a zoom ratio, only electrons in the zoom area 40 are processed in a circuitry section by a low-frequency clock signal to compose images of a display part.
By electrons generated and condensed in all pixels of a signal line of the A and B region in an electronic zoom mode, a large quantity of electrons rapidly transferred to the horizontal transfer stage 30 can be discharged through a reset drain of an output terminal along the stage 30. Since a quantity of inflow electrons is temporarily greater than a discharge capacity of the horizontal transfer stage 30, an effective potential of the stage 30 is rapidly lowered. As a result, a part of the electrons transferred to the stage 30 flows backwardly toward all the vertical transfer stages, as shown in a backflow area 30 of FIG. 3.
The backflow electrons are mixed with electrons of the zoom area 40. This causes a blooming phenomenon in which normal zoom images are not expressed in an upper scanning line of a display screen and the overall screen becomes bright.
FIG. 4A depicts a horizontal transfer area and an adjacent field insulation area in a conventional solid state imaging device. FIG. 5A through FIG. 5C are diagrams for describing formation of such a conventional solid state imaging device.
Referring to FIG. 5A, a thin gate insulating layer 105 is formed over a semiconductor substrate 117. On the insulating layer 105, ionized impurities are implanted to form a P-type well 111, a P-type impurity doping layer 109, a peripheral well 115, and a horizontal charge stop layer 113. Thus, a lower structure of an impurity doping layer is made.
Then, a field insulating layer 103 is stacked on an overall surface of the substrate 117 in which doping layers are formed. The field insulating layer 103 remains only in a field insulation part as the result of conventional patterning, thus distinguishing an active region from the filed insulation part.
Referring to FIG. 5B, a photoresist pattern 119 is used as an ion-implanting mask to selectively implant N-type impurities into the semiconductor substrate 117, thereby forming a transfer stage such as a horizontal transfer stage 107. Conventionally, an amount (dosage) of ionized impurities is 3xc3x97102xcx9c5xc3x971012 particles/cm2.
Referring to FIG. 5C, a gate electrode 101 made of polysilicon is formed over the semiconductor substrate 117 in which an impurity doping has been carried out. The gate electrode 101 is vertical to a migration direction of a horizontal transfer stage 107. Conventionally, a gate electrode is classified into two groups. By way of a patterning step, one of the two groups is formed first. After implanting low-concentration impurities of 2xc3x971011xcx9c4xc3x971011 particle/cm2 into a gate electrode of the firstly formed group, a gate electrode of the other group is formed. Gate electrodes of the secondly formed group are each partially overlapped between the firstly formed groups. A step of forming a thin insulating layer is carried out between the steps of forming the two groups of gate electrodes to thereby insulate the gate electrode groups from each other.
Turning to FIG. 4A, a thin insulating layer 105 is formed over the semiconductor substrate 117. An interface 100xe2x80x2 is formed between a horizontal transfer area 100 and a filed insulation part 400. A filed insulating layer 103 is formed on a gate insulating layer 105 of the filed insulation part 400. A conductive layer 101 is formed on the gate insulating layer 105 from the horizontal transfer area 100 to the interface 100xe2x80x2, and on the field insulating layer 103 from the field insulation part 400. The field insulating layer 103 increases in thickness from a boundary of the filed insulation part 400 to an external periphery at a constant rate, and then maintains a constant thickness. The conductive layer, i.e., gate electrode 101 spreads considerably over the horizontal transfer region 100 and the field insulation part 400.
An N-type impurity doping layer composing a horizontal transfer stage 107, a P-type impurity doping layer 109, and a P-type well 111 are formed under a surface layer of the semiconductor substrate 117. A horizontal charge stop layer 113 and the P-type well 111 are formed under the field insulating layer 400 and the interface 100xe2x80x2. The horizontal charge stop layer 113 is doped with P-type impurities. A P-type peripheral well 115 is formed at the substrate 117.
FIG. 4B illustrates the charge variation the line X-Xxe2x80x2 of FIG. 4A. The line X1 of FIG. 4B represents a potential when a voltage is not applied to a gate electrode, and line X2 of FIG. 4B represents a increased potential when a voltage is applied to a gate electrode. As shown, there is no charge carrier (i.e., construction capable of passing or receiving electrons) in an interface and a field insulation part. If transferred electrons increases in number, a horizontal transfer stage cannot process all the transferred electrons using a normal screen processing method. Remnant electrons accumulate in the horizontal transfer stage and lower an effective potential, and flow backwardly toward a vertical transfer stage. The backflow electrons are mixed with electrons which represent a zoom area image, causing a blooming phenomenon in an upper screen part.
The blooming phenomenon can be explained with reference to FIG. 6 and FIG. 4C. Steps in these diagrams denote a potential difference of each part when a gate electrode is overlapped with a horizontal transfer stage. The lower the steps, the higher their potentials. With a higher potential, electrons can rise up well.
The structures of solid state imaging devices in the previously discussed U.S. patents are directed to the prevention of problems caused by excessive electron generation in a light receiving part. These patents do not consider surplus electrons based on an image function, i.e., an electronic zooming function. In other words, the patents do not consider discharge direction or path of electrons in view of batch discharging and processing of photoelectrons generated in a predetermined area of a solid state imaging device.
Therefore, conventional structures do not overcome the blooming phenomenon that occurs in a solid state imaging device having an electronic zooming function.
It is therefore an object of the present invention to provide a solid state imaging device which can prevent a blooming phenomenon in a displayed screen even though photoelectrons generated in a light receiving part are transferred to a horizontal transfer stage in an electronic zoom mode at a same time, and to provide a method of forming the same.
It is another object of the invention to provide a solid state imaging device which can prevent a blooming phenomenon therein while performing an electronic zooming function and suppress image distortion when electrons of an area which compose images deviate from a horizontal transfer stage, and to provide a method of forming the same.
It is still another object of the invention to provide a solid state imaging device having an electronic zooming function and a structure which can easily secure a sufficient processing margin, and to provide a method of forming the same.
According to one aspect of the present invention, a charge-coupled-device (CCD) solid state imaging device includes a semiconductor substrate having a surface defined by an active area and a field insulating area, a plurality of light receiving parts arranged in a matrix of rows and columns within the active area of the surface of the semiconductor substrate, a plurality of vertical charge transfer stages which extend parallel to each other in a column direction and which are connected to adjacent respective columns of the plurality of light receiving parts, and a horizontal charge transfer stage commonly connected to ends of the plurality of vertical transfer stages and formed in a horizontal transfer area. The horizontal transfer area includes an insulating layer and a conductor formed sequentially over the surface of the semiconductor substrate, and a first impurity layer of a first conductivity type and a second impurity layer of a second conductively type formed sequentially under the surface of the semiconductor substrate. A barrier area is located adjacent the horizontal transfer area and spaced from the field insulating area. The barrier area includes the insulating layer and the conductor extending from the horizontal transfer area over the surface of the semiconductor substrate, a barrier area of the second conductivity type formed under the surface of the semiconductor substrate and adjacent the first impurity layer of the horizontal transfer area, and the second impurity layer extending from the horizontal transfer area and formed under the barrier area. A discharge area is located between the barrier area and the field insulating area. The discharge area includes a field insulating layer interposed between the insulating layer and the conductor extending from the barrier area over the surface of the semiconductor substrate, and a discharge layer of the first conductivity type formed under the surface of the semiconductor substrate and adjacent the barrier layer of the barrier area. An impurity concentration of the discharge layer is greater than that of the first impurity layer.
According to another aspect of the present invention, there is provided a method forming an interface between a horizontal charge transfer stage and an field insulating area of a solid state imaging device formed on a semiconductor substrate. The semiconductor substrate is selectively doped with impurities of a second conductivity type to form a lower structure having a field insulating area defined on a surface thereof. A discharge layer is formed in a discharge area of the lower structure which is adjacent to the field insulating area by doping with impurities of a first conductivity type at a first concentration. A field insulating layer is formed over the field insulation area of the surface of the lower structure. A barrier layer is formed in a barrier area of the lower structure which is adjacent to the discharge area by doping with impurities of the second conductivity type. The discharge area is interposed between the barrier area and the field insulating area. An impurity layer is formed in a horizontal charge transfer area of the lower structure which is adjacent to the barrier area by doping with impurities of the first conductivity type at a second concentration which is lower than the first concentration. The barrier area is interposed between the horizontal charge transfer area and the discharge area.